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FS5502 Datasheet(PDF) 41 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Name Address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 OTP_CFG_UVOV_1 0A VCORE_V[7:0] OTP_CFG_UVOV_2 0B VDDIOOVTH[3:0] VCOREOVTH[3:0] OTP_CFG_UVOV_3 0C 0 0 VDDIO_V VCORE_SVS_CLAMP[4:0] OTP_CFG_UVOV_4 0D 0 0 0 0 VMON1OVTH[3:0] OTP_CFG_UVOV_5 0E 0 0 0 0 0 0 0 0 OTP_CFG_UVOV_6 0F VDDIOUVTH[3:0] VCOREUVTH[3:0] OTP_CFG_UVOV_7 10 0 0 0 0 VMON1UVTH[3:0] OTP_CFG_UVOV_8 11 0 0 0 0 0 0 0 0 OTP_CFG_PGOOD 12 0 PGOOD_ RSTB 0 0 0 PGOOD_ VMON1 PGOOD_ VDDIO PGOOD_ VCORE OTP_CFG_ABIST1 13 0 0 0 0 0 0 0 0 OTP_CFG_ASIL 14 1 0 0 0 0 0 0 VMON1_EN OTP_CFG_I2C 15 0 0 0 0 FS_I2CDEVADDR[3:0] OTP_CFG_DGLT_DUR_1 16 0 0 VCORE_UV_DGLT[1:0] VCORE_ OV_DGLT VDDIO_UV_DGLT[1:0] VDDIO_ OV_DGLT OTP_CFG_DGLT_DUR_2 17 0 0 0 0 0 VMON1_UV_DGLT[1:0] VMON1_ OV_DGLT Table 58. Fail-safe OTP_REGISTERS 12.2 Main OTP bit description Address Register Bit Symbol Value Description VPRE output voltage 01 0111 4.1 V 14 OTP_CFG_VPRE_1 5 to 0 VPREV[5:0] 10 0000 5.0 V VPRE slope compensation 00 0100 40 mV/µs 00 0101 50 mV/µs 00 0110 60 mV/μs 00 0111 70 mV/μs 00 1000 80 mV/µs 00 1001 90 mV/µs 00 1010 100 mV/μs 00 1110 140 mV/μs 01 0001 170 mV/μs 01 0100 200 mV/μs 15 OTP_CFG_VPRE_2 5 to 0 VPRESC[5:0] 01 1000 240 mV/μs VPRE current limitation threshold 00 50 mV 01 80 mV 10 120 mV 7 to 6 VPREILIM[1:0] 11 150 mV VPRE low-side slew rate control 3 to 2 VPRESRLS[1:0] 11 PU/PD/900 mA VPRE high-side slew rate control 00 PU/PD/130 mA 01 PU/PD/260 mA 10 PU/PD/520 mA 16 OTP_CFG_VPRE_3 1 to 0 VPRESRHS[1:0] 11 PU/PD/900 mA Table 59. Main OTP bit description FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 41 / 113 |
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