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FS5502 Datasheet(PDF) 66 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO 16.2 Application schematic INTERNAL COMPENSATION aaa-033202 DRIVER BUCK3_SW BUCK3_FB EPAD BUCK3_IN BUCK3_INQ COUT_BUCK3 CIN_BUCK3 LBUCK3 VPRE VBUCK3 CONTROLLER BUCK3 Figure 18. BUCK3 schematic 16.3 Compensation network and stability The internal compensation network ensures the stability and the transient response performance of the buck converter. OTP_VB3INDOPT[1:0] scales the slope compensation and the zero cross detection according to inductor value. 1.0 μH is the recommended inductor value for BUCK3. Use case with VPRE = 4.1 V, VBUCK3 = 2.3 V, LVBUCK3 = 1.0 μH, VBUCK3_SW = 2.22 MHz, COUT_BUCK3 = 44 μF Use case stability verification • Phase margin target PM > 45° and gain margin target GM > 6 dB. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 66 / 113 |
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