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FS5502 Datasheet(PDF) 59 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 59 Page - NXP Semiconductors |
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59 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO VPRE MOSFET switching time can be estimated to TSW = (QGD + QGS / 2) / IPRE_GATE_DRV using the gate charge definition from Figure 12. QGD and QGS can be extracted from the MOSFET data sheet. aaa-030992 VDS ID VGS(pl) VGS VGS(th) QGS2 QGS QG(tot) QGD QGS1 Figure 12. MOSFET gate charge definition 14.6 VPRE efficiency VPRE efficiency versus current load is given for information based on external component criteria provided and VSUP voltage 14 V. If the conditions change, it has to be recalculated with the FS5502_PDTCAL tool. The real efficiency has to be verified by measurement at the application level. Current (A) 0 1 3 5 7 VPRE Efficiency 9 8 10 6 4 2 aaa-035376 Efficiency (%) 65 455 kHz_5 V 455 kHz_4.1 V 455 kHz_3.3 V 2.22 MHz_5 V 2.22 MHz_4.1 V 2.22 MHz_3.3 V Fpre Ext. C and L Ext. MOSFET's 455 2220 Cin 47 47 ESR Cin VPRE at 455 kHz: BUK9K18-40E VPRE at 2.22 MHz: BUK9K25-40E 30 30 Cout 66 44 ESR Cout 10 10 L coil 6.8 2.2 GHS_drive 5 5 HS_Rdson 17 24 HS_QGtot 7 5 HS_QGD 3 2.4 HS_QGS 2 1.4 HS_Igate 900 900 THS_sw 5 4 GLS_drive 5 5 LS_Rdson 17 24 LS_QGtot 7 5 LS_QGD 3 2.4 LS_QGS 2 1.4 LS_Igate 900 900 TLS_sw 5 4 kHz µF mΩ µF mΩ µH DCR coil 25 25 Rshunt 10 10 mΩ mΩ V mΩ nC nC nC mA ns V mΩ nC nC nC mA LS_QRR 16 7.6 nC ns 67.5 70 72.5 75 77.5 80 82.5 85 87.5 90 92.5 95 97.5 100 Figure 13. VPRE theoretical efficiency FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 59 / 113 |
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