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FS5502 Datasheet(PDF) 4 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO 7 Pinning information 7.1 Pinning aaa-033197 PRE_CSP 42 PRE_COMP 41 n.c. 40 BUCK1_FB 39 PSYNC 38 BUCK1_SW 37 BUCK1_IN 36 35 34 INTB 33 32 n.c. 31 n.c. n.c. n.c. n.c. n.c. 30 29 WAKE2 1 n.c. n.c. 2 BUCK3_INQ 3 VDDI2C 4 5 BUCK3_IN 6 BUCK3_SW EXPOSED PAD 7 DBG 8 BUCK3_FB 9 SCL 10 SDA 11 n.c. 12 n.c. 13 n.c. 14 Figure 3. Pin configuration for HVQFN56 7.2 Pin description See Section 7.3 for connection of unused pins. Symbol Pin Type Description WAKE2 1 A_IN / D_IN Wake-up input 2 An external serial resistor is required if WAKE2 is a global pin n.c. 2 n.c. Not connected pin BUCK3_INQ 3 A_IN Low voltage BUCK3 quiet input voltage VDDI2C 4 A_IN Input voltage for I2C buffers n.c. 5 n.c. Not connected pin BUCK3_IN 6 A_IN Low voltage BUCK3 input voltage BUCK3_SW 7 A_OUT Low voltage BUCK3 switching node DBG 8 A_IN Debug mode entry BUCK3_FB 9 A_IN Low voltage BUCK3 voltage feedback Table 2. Pin description FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 4 / 113 |
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