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FS5502 Datasheet(PDF) 78 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 78 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
19.4 PSYNC for FS5502 and external PMIC
When PSYNC is used to synchronize one FS5502 and one external PMIC, PSYNC pin of
FS5502 is connected to PGOOD pin of the external PMIC.
When the external PMIC is PF82 from NXP, it can be pulled up to VSNVS pin of PF82.
In this configuration, FS5502 state machine stops after VPRE starts and waits for the
PGOOD pin of the external PMIC to be released to continue its own power sequencing. It
allows to synchronize the power up sequence of both devices.
During power-down sequence, FS5502 should wait for the external PMIC power-down
sequence completion before turning OFF VPRE (VPRE is powering the external PMIC).
OTP_VPRE_off_dly bit is configured to extend VPRE turn OFF delay from 250 µs default
value to 32 ms.
aaa-033206
sync_in
to digital
FS5502
PF82
PSYNC
PGOOD
sync_out
from digital
VSNVS
PSYNCIPD
PSYNCRPU
PSYNCCOUT
LOGIC
Figure 26. Synchronization of one FS5502 and one external PMIC (PF82)
aaa-033207
PF82 PGOOD release
FS5502 VPRE starts
VSUP
PSYNC
FS5502 VREGx
PF82 PGOOD
FS5502 VPRE
PF82 VREGx
FS5502 Sync_in
FS5502 Sync_out
T
When FS5502 VPRE starts, FS5502 waits for PSYNC
to be released by PF82 PGOOD before
continuing its own power-up sequence.
Regardless of the PF82 power-up sequence duration
( T), PSYNC synchronization allows
sequential power-up sequencing.
Figure 27. FS5502 and one PF82 synchronization timing diagram
TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min
Typ
Max
Unit
PSYNCVIL
Low level input voltage threshold
1
—
—
V
Table 74. PSYNC electrical characteristics
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
78 / 113



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