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FS5502 Datasheet(PDF) 71 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO 17.3 LDO1 electrical characteristics TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit VLDO1_IN Input voltage range 2.5 — 6.5 V VLDO1 Output voltage (OTP_VLDO1V[2:0]) 1.1 V, 1.2 V, 1.6 V, 1.8 V, 2.5 V, 2.8 V, 3.3 V, 5.0 V 1.1 — 5.0 V VLDO1_ACC_150 Output voltage accuracy, 150 mA current capability −2 — +2 % VLDO1_ACC_400 Output voltage accuracy, 400 mA current capability −3 — +3 % VLDO1_DROP_150 Minimum voltage drop for 150 mA current capability 0.5 — — V VLDO1_DROP_400 Minimum voltage drop for 400 mA current capability 1.0 — — V CIN_LDO1 Input capacitor (close to LDO1_IN pin) 1.0 — — μF COUT_LDO1_150 Output capacitor, 150 mA current capability 4.7 — 10 μF COUT_LDO1_400 Output capacitor, 400 mA current capability 6.8 — 10 μF COUT_LDO1 Output decoupling capacitor 0.1 — — μF VLDO1_LTR_150 Transient load regulation (from 10 mA to 150 mA in 2.0 μs) −4 — +4 % VLDO1_LTR_400 Transient load regulation (from 10 mA to 400 mA in 4.0 μs) −5 — +5 % VLDO1_LR Line regulation — — 0.5 % VLDO1_ILIM_150 Current limitation, 150 mA current capability (OTP_ LDO1ILIM) 200 280 500 mA VLDO1_ILIM_400 Current limitation, 400 mA current capability (OTP_ LDO1ILIM) 430 560 800 mA VLDO1_SOFT_START Soft start (enable to 90 %) — 1.0 1.3 ms VLDO1_STARTUP Overshoot at startup — — 2 % RLDO1_DISCH Discharge resistance (when LDO1 is disabled) 10 20 60 Ω TSDLDO1 Thermal shutdown threshold 160 — — °C TSDLDO1_HYST Thermal shutdown threshold hysteresis — 9 — °C TLDO1_TSD Thermal shutdown filtering time 3 5 8 μs Table 66. LDO1 electrical characteristics 18 Clock management 18.1 Clock description The clock management block is made of the Internal oscillator, the Phase Locked Loop (PLL) and multiple dividers. This block manages the clock generation for the internal digital state machines, the switching regulators and the external clock synchronization. The internal oscillator is running at 20 MHz by default after start up. The frequency is programmable by I2C and a spread spectrum feature can be activated by I2C to reduce the emission of the oscillator fundamental frequency. VPRE switching frequency comes from CLK2 (455 kHz) or CLK1 (2.22 MHz). BUCK1 and BUCK3 switching frequency comes from CLK1 (2.22 MHz). The switching regulators can be synchronized with an external frequency coming from FIN pin. A dedicated watchdog monitoring is implemented to verify and report the correct FIN frequency range. Different clocks can be sent to FOUT pin to synchronize an external IC or for diagnostic. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 71 / 113 |
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