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FS5502 Datasheet(PDF) 43 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 43 Page - NXP Semiconductors |
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43 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Address Register Bit Symbol Value Description BUCK1 compensation network 001 16.25 GM 010 32.5 GM 011 48.75 GM 100 65 GM 101 81.25 GM 4 to 2 VB1GMCOMP[2:0] 110 97.5 GM BUCK3 current limitation 01 2.6 A 1F OTP_CFG_BUCK3_2 1 to 0 VB3SWILIM[1:0] 11 4.5 A VLDO1 current limitation 0 400 mA 3 LDO1ILIM 1 150 mA VLDO1 output voltage 000 1.1 V 001 1.2 V 010 1.6 V 011 1.8 V 100 2.5 V 101 2.8 V 110 3.3 V 20 OTP_CFG_LDO 2 to 0 LDO1V[2:0] 111 5.0 V BUCK1 sequencing slot 000 Regulator start and stop in Slot 0 001 Regulator start and stop in Slot 1 010 Regulator start and stop in Slot 2 011 Regulator start and stop in Slot 3 100 Regulator start and stop in Slot 4 101 Regulator start and stop in Slot 5 110 Regulator start and stop in Slot 6 21 OTP_CFG_SEQ_1 2 to 0 VB1S[2:0] 111 Regulator does not start (enabled by I2C) LDO1 sequencing slot 000 Regulator start and stop in Slot 0 001 Regulator start and stop in Slot 1 010 Regulator start and stop in Slot 2 011 Regulator start and stop in Slot 3 100 Regulator start and stop in Slot 4 101 Regulator start and stop in Slot 5 110 Regulator start and stop in Slot 6 22 OTP_CFG_SEQ_2 2 to 0 LDO1S[2:0] 111 Regulator does not start (enabled by I2C) BUCK1 soft start/stop configurability 00 7.81 mV/µs 23 OTP_CFG_SEQ_3 7 to 6 DVS_BUCK1[1:0] 01 3.13 mV/µs Table 59. Main OTP bit description...continued FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 43 / 113 |
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