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FS5502 Datasheet(PDF) 65 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 65 Page - NXP Semiconductors |
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65 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Current (A) BUCK1 Efficiency (VPRE = 4.1 V) aaa-035374 Efficiency (%) 0.8 V_Eff 1.25 V_Eff 1.8 V_Eff Cin Ext. C and L Int. MOSFET's 60 µF ESR Cin 10 mΩ Cout 44 µF ESR Cout 10 mΩ L coil 1 µH DCR coil 20 mΩ HS_Rdson 135 mΩ QLS 0.5 nC QHS 0.5 nC THS_sw 3 ns GLS_drive 5 V GHS_drive 5 V LS_Rdson 80 mΩ TLS_sw 3 ns 0 2.5 2.0 1.0 1.5 0.5 2.25 1.75 0.75 1.25 0.25 90 85 95 100 80 Figure 17. BUCK1 theoretical efficiency 16 Low voltage buck: BUCK3 16.1 Functional description BUCK3 block is a low voltage, synchronous, peak current mode buck converter with integrated HS PMOS and LS NMOS. BUCK3 works in force PWM and the output voltage is configurable by OTP from 1.0 V to 3.3 V, the switching frequency is 2.22 MHz and the output current is limited to 3.6 A peak. The input of this block can be connected to the output of VPRE. The stability is ensured by an internal Type 2 compensation network with slope compensation. By default, BUCK3 switching frequency is derived from the internal oscillator, and can be synchronized with an external frequency signal applied on FIN input pin. The change from internal oscillator to external clock or vice versa is controlled by I2C. An overcurrent detection and a thermal shutdown are implemented on BUCK3 to protect the internal MOSFETs. The overcurrent induces a duty cycle reduction that could lead to the output voltage gradually dropping, causing an undervoltage condition. BUCK3 is part number dependent according to OTP_BUCK3EN bit. BUCK3_INQ pin, used to bias internal BUCK3 driver, and must be connected to the same source pin as BUCK3_IN pin. The ramp up and ramp down of BUCK3 when it is enabled and disabled is configurable with OTP_DVS_BUCK3[1:0] bits to accommodate multiple MCU soft start requirements. Programmable phase shift control is implemented, see Section 18 "Clock management". FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 65 / 113 |
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