FS5502 datasheet(88/113 Pages) NXP

88 / 113 page

NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

aaa-033209

TCOREMON_OV

VBUCK1 =

VCOREMON

= 0.75 V

VBUCK1 =

VCOREMON

= 0.8 V

I2C

FS_I_NOT_SVS

I2C

FS_I_SVS

VBUCK12_SVS

Figure 32. SVS principle

27.2.3 VDDIO monitoring

VDDIO input pin can be connected to VPRE, LDO1, BUCK3 or an external regulator.

The regulator connected to VDDIO must be at 3.3 V or 5.0 V to be compatible with

overvoltage and undervoltage monitoring thresholds. In order to turn OFF the regulator

in case of overvoltage detection, the configuration of which regulator is connected to

VDDIO is done with OTP_VDDIO_REG_ASSIGN[2:0] bits. If an external regulator (not

delivered by the FS5502) is connected to VDDIO, this regulator cannot be turned OFF,

but the overvoltage flag is reported to the MCU, which can take appropriate action. In all

cases, the reaction on RSTB is configured with VDDIO_OV/UV_FS_IMPACT[1:0] bits.

aaa-031023

bandgap_FS

OTP_VDDIOOVTH[3:0]

OTP_VDDIOUVTH[3:0]

OTP_VDDIO_V

VDDIO

Figure 33. VDDIO monitoring principle

When overvoltage or undervoltage fault is detected, the fail-safe reaction on RSTB is

configurable with the VDDIO_OV/UV_IMPACT[1:0] bits during the INIT_FS phase.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

88 / 113

FS5502 Datasheet(PDF) 88 Page - NXP Semiconductors