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FS5502 Datasheet(PDF) 12 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 12 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
aaa-032949
DBG
VDBG
I2C OTP pgm
I2C
VSUP1/2
>VSUP_UHV
WAKE1/2
>WAKE12VIH
I2C
OFF
ON
REGx
PWR UP
Figure 7. Debug mode entry
When the DBG pin is asserted low after TDBG without I2C command access, the device
starts with the internal OTP configuration.
If VDBG voltage is maintained at DBG pin, a new OTP configuration can be emulated or
programmed by I2C communication using NXP FlexGUI interface and NXP socket EVB.
When the OTP process is completed, the device starts with the new OTP configuration
when DBG pin is asserted low. The OTP emulation/programming is possible for during
engineering development only. The OTP programming in production is done by NXP only.
In OTP Debug mode (DBG = 5.0 V), the I2C address is fixed to 0x20 for the main digital
access and 0x21 for the fail-safe digital access.
TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground.
Symbol
Parameter
Min
Typ
Max
Unit
VDBG
Debug mode entry threshold
4.5
—
5.5
V
TDBG
Debug mode entry filtering time (minimum duration of DBG = VDBG
after VSUP > VSUP_UVH and WAKE1 or WAKE2 > WAKE12VIH)
7.0
—
—
ms
Table 4. Electrical characteristics
9 Register mapping
Address
Register
M/FS
Adr_5 Adr_4 Adr_3 Adr_2 Adr_1 Adr_0
R/W
I2C
Read / Write
Reference
M_FLAG
0
0
0
0
0
0
0
1/0
Read / Write
Section 10.3
M_MODE
0
0
0
0
0
0
1
1/0
Read / Write
Section 10.4
M_REG_CTRL1
0
0
0
0
0
1
0
1/0
Read / Write
Section 10.5
M_REG_CTRL2
0
0
0
0
0
1
1
1/0
Read / Write
Section 10.6
M_CLOCK
0
0
0
0
1
0
1
1/0
Read / Write
Section 10.7
M_INT_MASK1
0
0
0
0
1
1
0
1/0
Read / Write
Section 10.8
M_INT_MASK2
0
0
0
0
1
1
1
1/0
Read / Write
Section 10.9
M_FLAG1
0
0
0
1
0
0
0
1/0
Read / Write
Section 10.10
M_FLAG2
0
0
0
1
0
0
1
1/0
Read / Write
Section 10.11
M_VMON_REGX
0
0
0
1
0
1
0
1/0
Read / Write
Section 10.12
M_LVB1_SVS
0
0
0
1
0
1
1
1
Read only
Section 10.13
M_MEMORY0
0
1
0
0
0
1
1
1/0
Read / Write
Section 10.14
M_MEMORY1
0
1
0
0
1
0
0
1/0
Read / Write
Section 10.15
M_DEVICEID
0
1
0
0
1
0
1
1
Read only
Section 10.16
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
12 / 113



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