FS5502 datasheet(61/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

INTERNAL

COMPENSATION

aaa-033201

DRIVER

BUCK1_SW

BUCK1_FB

EPAD

BUCK1_IN

COUT_BUCK1

CIN_BUCK1

LBUCK1

VPRE

VBUCK1

CONTROLLER

BUCK1

Figure 14. BUCK1 standalone schematic

15.3 Compensation network and stability

The internal compensation network ensures the stability and the transient response

performance of the buck converter. The error amplifier gain is configurable with

OTP_VB1GMCOMP[2:0] bits for BUCK 1 regulator. It is recommended to use the default

value that covers most of the use cases.

Decreasing the gain reduces the regulation bandwidth and increase the phase and

gain margin but transient performance is degraded. Increasing the gain enlarges the

regulation bandwidth and improves the transient performance but the phase and gain

margin is degraded.

OTP_VB1INDOPT[1:0] scales the slope compensation and the zero cross detection

according to the inductor value. 1.0 μH is the recommended inductor value for BUCK1.

Use case with VPRE = 4.1 V, VBUCK1 = 1.0 V, LVBUCK1 = 1.0 μH, VBUCK1_SW =

2.22 MHz, COUT_BUCK1 = 44 μF, default Err Amp gain

Use case stability verification

• Phase margin target PM > 45° and gain margin target GM > 6 dB.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

61 / 113

FS5502 Datasheet(PDF) 61 Page - NXP Semiconductors