FS5502 datasheet(8/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

Name

Type

Connection if not used

GND

Connection mandatory

Table 3. Connection of unused pins...continued

8 Functional description

The FS5502 device has two independent logic blocks. The main state machine manages

the power management, the Standby mode and the wake-up sources. The fail-safe state

machine manages the voltage monitoring of the power management.

8.1 Simplified functional state diagram

aaa-033198

From any

FS_state

From any

M_state

From any

FS_state after

`8s TIMER'

From any FS_state

after `WAIT'

exclude `PGOOD'

PORB_FS=0 or FS_ENABLE=0

PORB_FS=1 and VBOS > VBOS_por

PGOOD=RSTB=0

Release PGOOD and RSTB

RSTB=PGOOD=0

RSTB=0,

PGOOD=1

FS_READY=1

PGOOD=RSTB=0

START 8s Timer if DBG=0

PGOOD=RSTB=0

Power Down

STANDBY

Wait 10 µs

FS_ENABLE=0

RSTB_DUR

expired

RSTB_DUR

expired

READY

FS_ENABLE=1

WAIT

(Vxx_uv=0 and Vxx_ov=0)

DEEP-FS

RELEASE

RESET

PGOOD=RSTB=1

INIT_FS

ASSERT

RSTB

Activate RSTB

From any FS_state

after `WAIT'

include `RSTB'

ASSERT

PGOOD

Activate PGOOD

PORB_MAIN=0 or VBOS < VBOS_por

PORB_MAIN=1

and VBOS > VBOS_por

and (WAKE1=1or WAKE2=1)

All regulators OFF

FS logic OFF

VPRE ON

VREGx PWR_UP

All regulators ON

VPRE > VPRE_uvh and VPRE_soft_start complete

and (PSYNC=1 or !OTP_PSYNC_cfg)

FS_ENABLE=1

VPRE < VPRE_uvl (2ms)

Power Down

STANDBY

(WAKE1=1 or WAKE2=1)

and DBG=0

WAKE1=WAKE2=0

WAKE1=1 and DBG=0

WAKE1=0 (1ms)

or OTP_

AutoRetry_4s

WAKE1=WAKE2=0

VPRE_FB_OV or

(VREGx_TSD and OTB_CONF_TSD)

All regulators OFF

FS logic OFF

DFS=1

Fail-safe State Machine

MAIN State Machine

WAIT

FS &

SUPPLY

STANDBY

DEEP-FS

VSUP > VSUP_uvh and VBOS > VBOS_uvh

and FS_READY=1 and

(PSYNC=1 or OTP_PSYNC_cfg)

VPRE ON

VREGx

PWR_UP

VPRE

OFF

End PWR_DOWN

VREGx OFF

VBOOST OFF

WAIT 250 µs

FS_ENABLE=0

VREGx PWR_DOWN

GoTo_STBY=1

or FS_READY=0

or (WAKE1=WAKE2=0)

VBOS < VBOS_uvl

or VPRE < VPRE_uvl

WAIT

OTP_VPRE_off_dly

VREGx

PWR_

DOWN

End PWR_UP

NORMAL_

Figure 4. Simplified functional state diagram

8.2 Main state machine

The FS5502 start when VSUP > VSUP_UVH and WAKE1 or WAKE2 > WAKE12VIH with

VBOS first, followed by VPRE, and the power-up sequencing from the OTP programming

for the remaining regulators if PSYNC pin is pulled up to VBOS. If during the power-up

sequence VSUP < VSUP_UVL, the device goes back to Standby mode. When the power-

up is finished, the main state machine is in Normal_M mode, which is the application

running mode with all the regulators ON and VSUP_UVL has no effect even if VSUP <

VSUP_UVL. See Figure 29 for the minimum operating voltage.

The power up sequence can be synchronized with another PMIC using the PSYNC pin

in order to stop before or after VPRE is ON and wait for the PMIC feedback on PSYNC

pin before allowing FS5502 to continue its power up sequence. If the power up sequence

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

8 / 113

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