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FS5502 Datasheet(PDF) 90 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 90 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
aaa-032960
UV
bandgap_FS
OTP_VMON1OVTH[3:0]
OTP_VMON1UVTH[3:0]
ext_R1
ext_R2
VREGx
VMON1
OV
Figure 34. VMON1 monitoring principle
The external resistor bridge connected to VMON1 shall be calculated to deliver a middle
point of 0.8V. It is recommended to use ±1 % or less resistor accuracy. When overvoltage
or undervoltage fault is detected, the fail-safe reaction on RSTB is configurable with the
VMON1_OV/UV_FS_IMPACT[1:0] bits during the INIT_FS phase.
VMONx_OV_FS_IMPACT[1:0]
VMON1 OV impact on RSTB
00
No effect on RSTB
01
Reserved
1x (default)
RSTB is asserted
Reset condition
POR
Table 86. VMONx error impact configuration
VMONx_UV_FS_IMPACT[1:0]
VMON1 UV impact on RSTB
00
No effect on RSTB
01 (default)
No effect on RSTB
1x
RSTB is asserted
Reset condition
POR
TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min
Typ
Max
Unit
VMON1_OV_min Overvoltage threshold minimum
—
+4.5
—
%
VMON1_OV_max Overvoltage threshold maximum
—
+12
—
%
VMON1_OV_step Overvoltage threshold step (OTP_
VMON1OVTH[7:0] bits)
—
+0.5
—
%
VMON1_OV_acc Overvoltage threshold accuracy
−2
—
2
%
20
25
30
μs
TMON1_OV
Overvoltage filtering time (OTP_
VMON1_OV_DGLT bit)
40
45
50
μs
VMON1_UV_min Undervoltage threshold minimum
—
−4.5
—
%
VMON1_UV_max Undervoltage threshold maximum
—
−12
—
%
Table 87. VMON1 (without ext resistor accuracy) electrical characteristics
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
90 / 113



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