FS5502 datasheet(54/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

aaa-030989

PRE_COMP

Vref

gmEA

frequency

Gain

gmEA x Rcomp

Fz = 1 /

(Rcomp x Ccomp)

Fpo = 1 /

(Ro x Ccomp)

Fp = 1 /

(Rcomp x Chf)

Fbw = Fsw /10

RCOMP CCOMP

CHF

PRE_FB

Figure 9. Type 2 compensation network concept

Calculation guideline

• System bandwidth for VPRE = 455 kHz: Fbw = FPRE_SW / 10

System bandwidth for VPRE = 2.22 MHz: Fbw = FPRE_SW / 15

• Compensation zero: Fz = Fbw / 10

• Compensation pole for VPRE = 455 kHz: Fp = FPRE_SW / 2

• Compensation pole for VPRE = 2.22 MHz: Fp = FPRE_SW / 4

• FGBW = 1 / (2π x RSHUNT x VPRE_LIM_GAIN x COUT_PRE)

• Error amplifier gain: EA_gain = (VREF / VPRE) x gmEAPRE x RCOMP = 10 ^ LOG (FBW /

FGBW)

• VREF = 1.0 V, RCOMP = VPRE x (EA_gain / gmEAPRE)

• CCOMP = 1 / (2π x Fz x RCOMP)

• CHF = 1 / (2π x Fp x RCOMP)

• Slope compensation: Se > (VPRE / LVPRE) x RSHUNT x VPRE_LIM_GAIN

The compensation network can be automatically calculated in the

FS5502_OTP_Config.xlsm file which is using the same formulas. A Simplis simulation is

recommended to verify the Phase and Gain Margin with normalized components.

Use case calculation with VPRE = 4.1 V, LVPRE = 6.8 μH, FPRE_SW = 455 kHz,

COUT_PRE = 66 μF, RSHUNT = 10.0 mΩ

• System bandwidth: Fbw = 45 kHz

• Compensation zero: Fz = 4.5 kHz

• Compensation pole: Fp = 227.5 kHz

• FGBW = 53 kHz

• Error amplifier gain: EA_gain = 10 ^ LOG (FBW / FGBW) = 0.86

• RCOMP = 2.34 kΩ = 2.2 kΩ

• CCOMP = 15.9 nF = 16 nF

• CHF = 318 pF = 330 pF

• Slope compensation: Se > 30 mV/μs

Use case stability verification

• Phase margin target PM > 45° and gain margin target GM > 6 dB.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

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