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FS5502 Datasheet(PDF) 27 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO 10.13 M_LVB1_SVS register Bit 23 22 21 20 19 18 17 16 Read RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset 0 0 0 0 0 0 0 0 Table 27. M_LVB1_SVS register bit allocation Bit 15 14 13 12 11 10 9 8 Read RESERVED RESERVED RESERVED LVB1_SVS[4:0] Reset 0 0 0 0 0 0 0 0 Bit Symbol Description Static voltage scaling negative offset 00000 0 mV 00001 −6.25 mV 00010 −12.50 mV 00011 −18.75 mV 00100 −25 mV 00101 −31.25 mV 00110 −37.5 mV 00111 −43.75 mV 01000 −50 mV 01001 −56.25 mV 01010 −62.5 mV 01011 −68.75 mV 01100 −75 mV 01101 −81.25 mV 01110 −87.5 mV 01111 −93.75 mV 10000 −100 mV 12 to 8 LVB1_SVS[4:0] Reset condition: POR Table 28. M_LVB1_SVS register bit description 10.14 M_MEMORY0 register Bit 23 22 21 20 19 18 17 16 Write MEMORY0[15:8] Read MEMORY0[15:8] Reset 0 0 0 0 0 0 0 0 Table 29. M_MEMORY0 register bit allocation FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 27 / 113 |
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