FS5502 datasheet(51/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

Address

Bit

Symbol

Value

Description

VCORE undervoltage filtering time

5 μs

15 μs

25 μs

5 to 4

VCORE_UV_DGLT[1:0]

40 μs

VCORE overvoltage filtering time

25 μs

VCORE_OV_DGLT

45 μs

VDDIO undervoltage filtering time

5 μs

15 μs

25 μs

2 to 1

VDDIO_UV_DGLT[1:0]

40 μs

VDDIO overvoltage filtering time

25 μs

OTP_CFG_DGLT_DUR_1

VDDIO_OV_DGLT

45 μs

VMON1 undervoltage filtering time

5 μs

15 μs

25 μs

2 to 1

VMON1_UV_DGLT[1:0]

40 μs

VMON1 overvoltage filtering time

25 μs

OTP_CFG_DGLT_DUR_2

VMON1_OV_DGLT

45 μs

Table 60. Fail-safe OTP bit description...continued

13 Best of supply

13.1 Functional description

VBOS regulator manages the best of supply from VSUP and VPRE to efficiently generate

5.0 V output to supply the internal biasing of the device. VBOS is also the supply of

VPRE high side.

VBOS undervoltage might not guarantee the full functionality of the device.

Consequently, VBOS_UVL detection powers down the device.

VSUP_UV7 undervoltage threshold is used to enable the path from VSUP to VBOS when

VSUP < VSUP_UV7 to have a low drop path from VSUP, while VPRE is going low and to

power up the device when VPRE is not started. When VSUP > VSUP_UV7, VBOS is forced

to use VPRE to optimize the efficiency.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

51 / 113

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