FS5502 datasheet(20/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

Bit

Symbol

Description

FOUT phase shifting configuration (see Section 18.2 "Phase shifting")

000

No shift

001

Shifted by 1 clock cycle of CLK running at 20 MHz

010

Shifted by 2 clock cycle of CLK running at 20 MHz

011

Shifted by 3 clock cycle of CLK running at 20 MHz

100

Shifted by 4 clock cycle of CLK running at 20 MHz

101

Shifted by 5 clock cycle of CLK running at 20 MHz

110

Shifted by 6 clock cycle of CLK running at 20 MHz

111

Shifted by 7 clock cycle of CLK running at 20 MHz

18 to 16

FOUT_PHASE[2:0]

Reset condition: POR

FOUT_clk frequency selection (CLK1 or CLK2)

FOUT_clk = CLK1

FOUT_clk = CLK2

FOUT_CLK_SEL

Reset condition: POR

Enable request of EXT FIN selection at PLL input

No effect

FIN selection request

EXT_FIN_SEL

Reset condition: POR

FIN input signal divider selection

Divider by 1

Divider by 6

FIN_DIV

Reset condition: POR

Modulation activation of main oscillator

Modulation disabled

Modulation enabled

MOD_EN

Reset condition: POR

11 to 8

CLK_TUNE[3:0]

See Table 67

Table 16. M_CLOCK register bit description...continued

10.8 M_INT_MASK1 register

Bit

Write

VPREOC_M

BUCK1OC_

BUCK3OC_

LDO1OC_M

Read

RESERVED VPREOC_M RESERVED

BUCK1OC_

RESERVED

BUCK3OC_

LDO1OC_M

RESERVED

Reset

Table 17. M_INT_MASK1 register bit allocation

FS5502

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Product data sheet

Rev. 4 — 27 October 2021

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