LMK04832PAPSLASHEM datasheet(25/103 Pages) TI

25 / 103 page

8.3.2 SYNC/SYSREF

The SYNC and SYSREF signals share the same SYNC/SYSREF Clock Distribution path. To properly use SYNC

and/or SYSREF for JESD204B/C it is important to understand the SYNC/SYSREF system. Figure 8-2 shows the

detailed diagram of a clock output block with SYNC circuitry included. Figure 8-3 shows the interconnects and

highlights some important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.

2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF

signal.

• If SYSREF block is being used, the SYSREF_PD bit must be clear.

• If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.

• For each CLKOUTx or CLKOUTy being used for SYSREF, the respective SCLKX_Y_PD bit must be

cleared.

3. DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits must be clear to power up the digital delay circuitry

used during SYNC to cause deterministic phase between the device clock dividers and the global SYSREF

divider.

4. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX

SYNC_DISX bit is clear.

5. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.

6. After these dividers are synchronized, the DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits may be set to

save current. Clearing them to power up may disrupt the output clock phase.

Table 8-2 shows the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 8-2. Some Possible SYNC Configurations

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

SYNC Disabled

CLKin0_DEMUX ≠ 0

No SYNC will occur.

Pin or SPI SYNC

CLKin0_DEMUX ≠ 0

Basic SYNC functionality, SYNC pin polarity is

selected by SYNC_POL.

To achieve SYNC through SPI, toggle the SYNC_POL

bit.

Differential input

SYNC

0 or 1

CLKin0_DEMUX = 0

Differential CLKin0 now operates as SYNC input.

JESD204B/C

Pulser on pin

transition.

SYSREF_PULSE_CNT

sets pulse count

Produce SYSREF_PULSE_CNT programmed

number of pulses on pin transition. SYNC_POL can

be used to cause SYNC through SPI.

JESD204B/C

Pulser on SPI

programming.

SYSREF_PULSE_CNT

sets pulse count

Programming SYSREF_PULSE_CNT register starts

sending the number of pulses.

Re-clocked SYNC

SYSREF operational,

SYSREF Divider as

required for training frame

size.

Allows precise SYNC for n-bit frame training patterns

for non-JESD converters such as LM97600.

External SYSREF

request

SYSREF_REQ_EN = 1

Pulser powered up

When SYNC pin is asserted, continuous SYSERF

pulses occur. Turning on and off of the pulses is

synchronized to prevent runt pulses from occurring on

SYSREF.

Continuous

SYSREF

SYSREF_PD = 0

SYSREF_DDLY_PD = 0

SYSREF_PLSR_PD = 1

(1)

Continuous SYSREF signal.

www.ti.com

LMK04832-SEP

SNAS838 – OCTOBER 2022

Submit Document Feedback

Product Folder Links: LMK04832-SEP

LMK04832PAP/EM Datasheet(PDF) 25 Page - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL