LMK04832PAPSLASHEM datasheet(85/103 Pages) TI

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The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by

lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window

size, then the lock count value is reset to 0.

9.1.2.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000. Then, the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs.

9.1.3 Driving CLKIN AND OSCIN Inputs

9.1.3.1 Driving CLKIN and OSCIN PINS With a Differential Source

CLKin and OSCin pins can be driven by differential signals. TI recommends setting the input mode to bipolar

(CLKinX_BUF_TYPE = 0) when using differential reference clocks. The device internally biases the input pins so

the differential interface should be AC-coupled. The recommended circuits for driving the CLKin pins with either

LVDS or LVPECL are shown in Figure 9-1 and Figure 9-2.

LVDS

Output

Input

100

Trace

(Di eren al)

0.1 µF

CLKINx_P

CLKINx_N

Figure 9-1. CLKINx_P/CLKINx_N or OSCIN Termination for an LVDS Reference Clock Source

LVPECL

Output

Input

100

Trace

(Di eren al)

0.1 µF

CLKINx_P

CLKINx_N

Figure 9-2. CLKINx_P/CLKINx_N or OSCIN Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKIN pins using

the following circuit. Note: the signal level must conform to the requirements for the CLKIN pins listed in the

Electrical Characteristics table.

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 85 Page - Texas Instruments