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LMK04832PAP/EM Datasheet(PDF) 55 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  103 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 55 Page - Texas Instruments

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8.6.2.3.5 SYSREF_PULSE_CNT
This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See SYSREF_REQ_EN,
SYNC_BYPASS, SYSREF_MUX for further description of SYSREF's outputs.
Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by
SYSREF_MUX and SYSREF functionality is powered up.
Table 8-34. Register 0x13E
BIT
NAME
POR DEFAULT
DESCRIPTION
7:2
NA
0
Reserved
1:0
SYSREF_PULSE_CNT
3
Sets the number of SYSREF pulses generated when not in continuous mode.
See SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX for more
information on SYSREF modes.
Field Value
Number of Pulses
0 (0x00)
1 pulse
1 (0x01)
2 pulses
2 (0x02)
4 pulses
3 (0x03)
8 pulses
8.6.2.3.6 PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
This register controls the feedback feature.
Table 8-35. Register 0x13F
BIT
NAME
POR DEFAULT
DESCRIPTION
7
PLL2_RCLK_MUX
0
Selects the source for PLL2 reference.
0: OSCIN
1: Currently selected CLKIN.
6
NA
0
Reserved
5
PLL2_NCLK_MUX
0
Selects the input to the PLL2 N Divider
0: PLL2 Prescaler
1: Feedback Mux
4:3
PLL1_NCLK_MUX
0
Selects the input to the PLL1 N Divider.
0: OSCIN
1: Feedback Mux
2: PLL2 Prescaler
2:1
FB_MUX
0
When in 0-delay mode, the feedback mux selects the clock output to be fed
back into the PLL1 N Divider.
Field Value
Source
0 (0x00)
CLKOUT6
1 (0x01)
CLKOUT8
2 (0x02)
SYSREF Divider
3 (0x03)
External
0
FB_MUX_EN
0
When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback
mux.
0: Feedback mux powered down
1: Feedback mux enabled
www.ti.com
LMK04832-SEP
SNAS838 – OCTOBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMK04832-SEP



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