LMK04832PAPSLASHEM datasheet(27/103 Pages) TI

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d. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLK0_1_DDLY_PD = 0,

DCLK2_3_DDLY_PD = 0, DCLK4_5_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0,

SYSREF_PULSE_CNT = 1 (2 pulses). SCLK0_1_PD = 0, SCLK2_3_PD = 0, SCLK4_5_PD = 0.

e. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B/C:

a. Set device clock and SYSREF divider digital delays: DCLK0_1_DDLY, DCLK2_3_DDLY,

DCLK4_5_DDLY, and SYSREF_DDLY.

b. Set device clock digital delay half steps: DCLK0_1_HS, DCLK2_3_HS, DCLK4_5_HS.

c. Set SYSREF clock digital delay as required to achieve known phase relationships: SCLK0_1_DDLY,

SCLK2_3_DDLY, and SCLK4_5_DDLY. If half step adjustments are required SCLK0_1_HS,

SCLK2_3_HS, and SCLK4_5_HS.

d. To allow SYNC to affect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0,

SYNC_DISSYSREF = 0.

e. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0.

3. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for

SYSREF to reset it's own divider or the dividers of the output clocks.

a. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,

SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay.

a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path clocks after

SYSREF_PD = 0.

5. Set SYSREF operation.

a. Allow pin SYNC event to start pulser: SYNC_MODE = 2.

b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. Complete! Assert the SYNC pin or toggle the SYNC_POL to send a series of 2 SYSREF pulses.

8.3.3.1.2 SYSREF_CLR

The local digital delay of the SCLKX_Y_DDLY is implemented as a shift buffer. To ensure no unwanted

pulses occur at this SYSREF output at start-up, when using SYSREF, requires clearing the buffers by setting

SYSREF_CLR = 1 for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF

output is used.

If the SYSREF pulser is used. It is also required to set SYSREF_CLR = 1 for 15 VCO clock cycles after the

SYSREF pulser is powered up.

8.3.3.2 SYSREF Modes

8.3.3.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming.

This implements the gapped periodic functionality of the JEDEC JESD204B/C specification.

When in SYSREF Pulser mode, the user can adjust the SYSREF_PULSE_CNT field in register 0x13E to

program the pulser to send out a set number of pulses.

8.3.3.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

Note

TI does not recommend continuous operation of the SYSREF clock due to crosstalk from the SYSREF

clock to device clock. JESD204B/C is designed to operate with a single burst of pulses to initialize the

system at start-up, after which it is theoretically not required to send another SYSREF because the

system will continue to operate with deterministic phases.

8.3.3.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses

using the SYNC/SYSREF_REQ pin.

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 27 Page - Texas Instruments

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