LMK04832PAPSLASHEM datasheet(29/103 Pages) TI

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8.3.4.2 Dynamic Digital Delay

Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the

clock signal.

For the device clock dividers this is accomplished by substituting the regular clock divider with an alternate divide

value of one larger than the regular divider for one cycle. This substitution will occur a number of times equal to

the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.

For the SYSREF divider, an alternate divide value is substituted for the regular divide value. This substitution will

occur a number of times equal to the value programmed into the DDLYd_STEP_CNT if DDLYd_SYSREF_EN

= 1. To achieve one cycle delay as is done for the device clock dividers, set the SYSREF_DDLY value to one

greater than SYSREF_DIV+SYSREF_DIV/2. For example, for a SYSREF divider of 100, to achieve 1 cycle

delay, SYSREF_DIV = 100 + 50 + 1 = 151.

While using the Dynamic Digital Delay feature, CLKin_OVERRIDE must be set to 0.

• By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with

respect to the other clocks.

• By programming a smaller alternate divider (delay) value, the phase of the adjusted outputs are advanced

with respect to the other clocks.

8.3.4.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay

of one VCO cycle occurs between CLKOUT2 and CLKOUT0. In the second adjustment, two delays of one VCO

cycle occur between CLKOUT2 and CLKOUT0. At this point in the example, CLKOUT2 is delayed three VCO

cycles behind CLKOUT0.

Assuming the device already has the following initial configurations:

• VCO frequency: 2949.12 MHz

• CLKOUT0 = 368.64 MHz, DCLK0_1_DIV = 8

• CLKOUT2 = 368.64 MHz, DCLK2_3_DIV = 8

The following steps illustrate the example above:

1. Set DCLK2_3_DDLY = 4. First part of delay for CLKOUT2.

2. Set DCLK2_3_DDLY_PD = 0. Enable the digital delay for CLKOUT2.

3. Set DDLYd0_EN = 0 and DDLYd2_EN = 1. Enable dynamic digital delay for CLKOUT2 but not CLKOUT0.

4. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 4, CLKOUT2 clock edge is aligned with CLKOUT0.

After step 4, CLKOUT2 counts nine clock distribution path cycles to the next rising edge, one greater than the

divider value, effectively delaying CLKOUT2 by one VCO cycle with respect to CLKOUT0. This is the first

adjustment.

5. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 5, CLKOUT2 clock edge was delayed one clock distribution path cycle from DCLKOUT0.

After step 5, CLKOUT2 counts nine clock distribution path cycles twice, each time one greater than the divide

value, effectively delaying CLKOUT2 by two clock distribution path cycles with respect to CLKOUT0. This is the

second adjustment.

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 29 Page - Texas Instruments

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