Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

LMK04832PAP/EM Datasheet(PDF) 62 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  103 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 62 Page - Texas Instruments

Back Button LMK04832PAP/EM Datasheet HTML 58Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 59Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 60Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 61Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 62Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 63Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 64Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 65Page - Texas Instruments LMK04832PAP/EM Datasheet HTML 66Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 62 / 103 page
background image
Table 8-43. Register 0x147 (continued)
BIT
NAME
POR DEFAULT
DESCRIPTION
3:2
CLKin1_DEMUX
0
Selects where the output of the CLKin1 buffer is directed.
Field Value
CLKin1 Destination
0 (0x00)
FIN
1 (0x01)
Feedback Mux (0-delay mode)
2 (0x02)
PLL1
3 (0x03)
Off
1:0
CLKin0_DEMUX
3
Selects where the output of the CLKin0 buffer is directed.
Field Value
CLKin0 Destination
0 (0x00)
SYSREF Mux
1 (0x01)
Reserved
2 (0x02)
PLL1
3 (0x03)
Off
8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
This register has CLKin_SEL0 controls.
Table 8-44. Register 0x148
BIT
NAME
POR DEFAULT
DESCRIPTION
7:6
NA
0
Reserved
5:3
CLKin_SEL0_MUX
0
This set the output value of the CLKin_SEL0 pin. This register only applies if
CLKin_SEL0_TYPE is set to an output mode
Field Value
Output Format
0 (0x00)
Logic Low
1 (0x01)
CLKin0 LOS
2 (0x02)
CLKin0 Selected
3 (0x03)
DAC Locked
4 (0x04)
DAC Low
5 (0x05)
DAC High
6 (0x06)
SPI Readback
7 (0x07)
Reserved
2:0
CLKin_SEL0_TYPE
2
This sets the IO type of the CLKin_SEL0 pin.
Field Value
Configuration
Function
0 (0x00)
Input
Input mode, see Input
Clock Switching -
Pin Select Mode for
description of input
mode.
1 (0x01)
Input with pullup resistor
2 (0x02)
Input with pulldown
resistor
3 (0x03)
Output (push-pull)
Output modes;
the CLKin_SEL0_MUX
register for description of
outputs.
4 (0x04)
Output inverted (push-
pull)
5 (0x05)
Reserved
6 (0x06)
Output (open-drain)
LMK04832-SEP
SNAS838 – OCTOBER 2022
www.ti.com
62
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LMK04832-SEP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com