LMK04832PAPSLASHEM datasheet(59/103 Pages) TI

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8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD,

SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to Figure 8-3 for block

diagram. Refer to Table 8-2 for using SYNC_MODE for specific SYNC use cases.

Table 8-39. Register 0x143

BIT

NAME

POR DEFAULT

DESCRIPTION

SYSREF_CLR

Except during SYSREF Setup Procedure (see SYNC/SYSREF), this bit should

always be programmed to 0. While this bit is set, extra current is used.

SYNC_1SHOT_EN

SYNC one shot enables edge sensitive SYNC.

0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC

is asserted.

1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC.

This results in the clock being held in SYNC for a minimum amount of time.

SYNC_POL

Sets the polarity of the SYNC pin.

0: Normal

1: Inverted

SYNC_EN

Enables the SYNC functionality.

0: Disabled

1: Enabled

SYNC_PLL2_DLD

0: Off

1: Assert SYNC until PLL2 DLD = 1

SYNC_PLL1_DLD

0: Off

1: Assert SYNC until PLL1 DLD = 1

1:0

SYNC_MODE

Sets the method of generating a SYNC event.

Field Value

SYNC Generation

0 (0x00)

Prevent SYNC Pin, SYNC_PLL1_DLD

flag, or SYNC_PLL2_DLD flag from

generating a SYNC event.

1 (0x01)

SYNC event generated from

SYNC pin or if enabled

the SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

2 (0x02)

For use with pulser - SYNC/

SYSREF pulses are generated by

pulser block via SYNC Pin or if

enabled SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

3 (0x03)

For use with pulser - SYNC/SYSREF

pulses are generated by pulser block

when programming register 0x13E

(SYSREF_PULSE_CNT) is written to

(see SYSREF_PULSE_CNT).

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 59 Page - Texas Instruments

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