LMK04832PAPSLASHEM datasheet(5/103 Pages) TI

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Table 5-1. Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

NAME

FIN0_P

ANLG

High-speed input for external VCO or clock distribution. Supports /2 for

frequency greater than 3250 MHz.

FIN0_N

VCC1_VCO

–

PWR

Power supply for VCO and clock distribution.

LDOBYP1

–

ANLG

LDO Bypass, bypassed to ground with 10-µF capacitor.

LDOBYP2

–

ANLG

LDO Bypass, bypassed to ground with a 0.1-µF capacitor.

CLKOUT3_P

Programmable

Clock output 3. For JESD204B/C systems suggest SYSREF Clock.

(2) Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

CLKOUT3_N

CLKOUT2_P

Programmable

Clock output 2. For JESD204B/C systems suggest Device Clock.

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

CLKOUT2_N

VCC2_CG1

–

PWR

Power supply for clock outputs 2 and 3.

CS#

CMOS

Chip Select

SCK

CMOS

SPI Clock

SDIO

I/O

CMOS

SPI Data

VCC3_SYSREF

–

PWR

Power supply for SYSREF divider and SYNC.

CLKOUT5_P

Programmable

Clock output 5. For JESD204B/C systems suggest SYSREF Clock.

(2) Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

CLKOUT5_N

CLKOUT4_P

Programmable

Clock output 4. For JESD204B/C systems suggest Device Clock.(2)

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

CLKOUT4_N

VCC4_CG2

–

PWR

Power supply for clock outputs 4, 5, 6 and 7.

CLKOUT6_P

Programmable

Clock output 6. For JESD204B/C systems suggest Device Clock.(2)

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

CLKOUT6_N

CLKOUT7_P

Programmable

Clock output 7. For JESD204B/C systems suggest SYSREF Clock.

(2) Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

CLKOUT7_N

STATUS_LD1

I/O

Programmable

Programmable status pin.

CPOUT1

ANLG

Charge pump 1 output.

DAP

–

GND

DIE ATTACH PAD, connect to GND.(1)

(1)

The metal lid is internally grounded and attached to the DAP.

(2)

Actual best allocation of device clocks and SYSREF depends upon frequency planning to group common frequencies.

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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