LMK04832PAPSLASHEM datasheet(31/103 Pages) TI

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Table 8-4. DCLK_DIV_ADJUST (continued)

DCLKX_Y_DIV

DCLK_DIV_ADJUST

3 (1)

–2

2 (1)

–2

(1)

Refer to the SYNC requirement SYNC/SYSREF

Table 8-5. DCLK_HS_ADJUST

DCLK & HS

DCLK_HS_ADJUST

For example: DCLKX_Y_DIV = 32, DCLKX_Y_DDLY = 10, DCC&HS = 1;

SYSREF_DDLY=10 – 1 + 0 + 1 – 2 = 8

8.3.6 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be selected

according to the combination of bits as illustrated in Figure 8-7.

CLKin_SEL_

AUTO_EN

CLKin_SEL_

PIN_EN

CLKin_SEL_

PIN_POL

Yes

Active CLKin is set by

CLKin_SEL_MANUAL

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins, inverted.

Yes

Active CLKin is set Auto

Mode State Machine

Yes

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins.

Input Clock Select

It is required for CLKin1

to be selected for

distribution mode.

Recommend using

CLKin_SEL_MANUAL

Figure 8-7. CLKINx Input Reference

The following sections provide information about how the active input clock is selected and what causes a

switching event in the various clock input selection modes.

8.3.6.1 Input Clock Switching - Manual Mode

When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 0, the active CLKin is selected by

CLKin_SEL_MANUAL. Programming a value of 0, 1, or 2 to CLKin_SEL_MANUAL causes CLKin0, CLKin1,

or CLKin2, respectively, to be the selected active input clock. In this mode, the EN_CLKinX bits are overridden

such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0.

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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