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LMK04832PAP/EM Datasheet(PDF) 81 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  103 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 81 Page - Texas Instruments

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8.6.2.9 (0x16F - 0x555) Misc Registers
8.6.2.9.1 PLL2_PRE_PD, PLL2_PD, FIN0_PD
Table 8-79. Register 0x173
BIT
NAME
POR DEFAULT
DESCRIPTION
7
N/A
0
Reserved
6
PLL2_PRE_PD
1
Powerdown PLL2 prescaler
0: Normal Operation
1: Powerdown
5
PLL2_PD
1
Powerdown PLL2
0: Normal Operation
1: Powerdown
4
FIN0_PD
1
Powerdown FIN0
0: Normal Operation
1: Powerdown
3:0
N/A
0
Reserved
8.6.2.9.2 PLL1R_RST
Refer to PLL1 R Divider Synchronization for more information on synchronizing PLL1 R divider.
Table 8-80. Register 0x177
BIT
NAME
POR DEFAULT
DESCRIPTION
7:6
NA
0
Reserved
5
PLL1R_RST
0
When set, PLL1 R divider will be held in reset. PLL1 will never lock with
PLL1R_RST = 1. This bit is used in when synchronizing the PLL1 R divider.
0: PLL1 R divider normal operation.
1: PLL1 R divider held in reset.
4:0
NA
0
Reserved
www.ti.com
LMK04832-SEP
SNAS838 – OCTOBER 2022
Copyright © 2022 Texas Instruments Incorporated
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