LMK04832PAPSLASHEM datasheet(30/103 Pages) TI

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CLKout0

368.64 MHz

CLKout2

368.64 MHz

First

Adjustment

VCO

2949.12 MHz

CLKout2

368.64 MHz

Second

Adjustment

DCLK2_3_DIV + 1

Figure 8-5. Single and Multiple Adjustment Dynamic Digital Delay Example

8.3.5 SYSREF to Device Clock Alignment

To ensure proper JESD204B/C operation, the timing relationship between the SYSREF and the Device clock

must be adjusted for optimum setup and hold time as shown in Figure 8-6. The global SYSREF digital delay

(SYSREF_DDLY), local SYSREF digital delay (SCLKX_Y_DDLY), local SYSREF half step (SCLKX_Y_HS), and

local SYSREF analog delay (SCLKX_Y_ADLY, SCLK2_3_ADLY_EN) can be adjusted to provide the required

setup and hold time between SYSREF and Device Clock. It is also possible to adjust the device clock

digital delay (DCLKX_Y_DDLY) and half step (DCLK0_1_HS, DCLK0_1_DCC) to adjust phase with respect

to SYSREF.

Figure 8-6. SYSREF to Device Clock Timing alignment

Depending on the DCLKout_X path settings, local SCLK_X_Y_DDLY might need adjustment factor. Following

equation can be used to calculate the required Digital Delay Values to align SYSREF to the corresponding

DCLKOUT

SYSREF_DDLY = DCLKX_Y_DDLY – 1 + DCLK_DIV_ADJUST + DCLK_HS_ADJUST – SCLK_X_Y_DDLY

(1)

SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1.

Table 8-4. DCLK_DIV_ADJUST

DCLKX_Y_DIV

DCLK_DIV_ADJUST

–1

LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 30 Page - Texas Instruments