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LMK04832PAP/EM Datasheet(PDF) 1 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 103 page ![]() LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner 1 Features • VID#: V62/22612 – Total ionizing dose 30 krad (ELDRS-free) – SEL immune >43 MeV × cm2/mg – SEFI immune >43 MeV × cm2/mg • Ambient temperature range: –55°C to 125°C • Maximum clock output frequency: 3255 MHz • Multi-mode: dual PLL, single PLL, and clock distribution • 6-GHz external VCO or distribution input • Ultra-low noise, at 2500 MHz: – 54-fs RMS jitter (12 kHz to 20 MHz) – 64-fs RMS jitter (100 Hz to 20 MHz) – –157.6-dBc/Hz noise floor • Ultra-low noise, at 3200 MHz: – 61-fs RMS jitter (12 kHz to 20 MHz) – 67-fs RMS jitter (100 Hz to 100 MHz) – –156.5-dBc/Hz noise floor • PLL2 – PLL FOM of –230 dBc/Hz – PLL 1/f of –128 dBc/Hz – Phase detector rate up to 320 MHz – Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz • Up to 14 differential device clocks – CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs • Up to 1 buffered VCXO/XO output – LVPECL, LVDS, 2xLVCMOS programmable • 1-1023 CLKOUT divider • 1-8191 SYSREF divider • 25-ps step analog delay for SYSREF clocks • Digital delay and dynamic digital delay for device clocks and SYSREF • Holdover mode with PLL1 • 0-delay with PLL1 or PLL2 2 Applications • Communications payloads • Radar imaging payload • Command and data handling 3 Description The LMK04832-SEP is a high performance clock conditioner with JEDEC JESD204B/C support for space applications. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high- performance outputs for traditional clocking systems. This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO. The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees. Package Information PART NUMBER PACKAGE(1) PACKAGE SIZE LMK04832-SEP HTQFP (64) (PAP0064E) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. CPOUT1 Control Registers STATUS_LD2 Device Control SYNC STATUS_LD1 RESET/GPO CLKIN_SEL0 CLKIN_SEL1 SCK SDIO CS# SPI CLKIN0 FIN0 Divider Pulser ÷1,÷2,..,÷1023 CLKIN0 CLKIN1/ FIN1/ FPCLKIN CLKIN2/ OSCOUT OSCIN CPOUT2 PLL1 CLKOUT0 CLKOUT1 CLKOUT12 CLKOUT13 14 Di eren al Outputs Input Switching/Holdover Phase Detector/ Charge Pump N Divider R Divider X2 N Divider FIN1 Phase Detector/ Charge Pump ÷2 Clock Distribution Path ÷1,÷2,..,÷1023 SYNC/SYSREF Distribution Path SYSREFDIV CLKOUT6 CLKOUT8 CLKIN1 PLL2 SYSREF/SYNC ... ... ... Switchable R Divider SYSREFDIV Block Diagram LMK04832-SEP SNAS838 – OCTOBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice. |
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