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LMK04832PAP/EM Datasheet(PDF) 70 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 103 page ![]() 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration 8.6.2.7.1 CLKin0_R Table 8-55. CLKin0_R[13:0] MSB LSB 0x153[5:0] / CLKin0_R[13:8] 0x154[7:0] / CLKin0_R[7:0] These registers contain the value of the CLKin0 divider. Table 8-56. Registers 0x153 and 0x154 REGISTER BIT NAME POR DEFAULT DESCRIPTION 0x153 7:6 NA 0 Reserved 0x153 5:0 CLKin0_R[13:8] 0 The value of PLL1 N counter when CLKin0 is selected. Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 0x154 7:0 CLKin0_R[7:0] 120 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 8.6.2.7.2 CLKin1_R Table 8-57. CLKin1_R[13:0] MSB LSB 0x155[5:0] / CLKin1_R[13:8] 0x156[7:0] / CLKin1_R[7:0] These registers contain the value of the CLKin1 R divider. Table 8-58. Registers 0x155 and 0x156 REGISTER BIT NAME POR DEFAULT DESCRIPTION 0x155 7:6 NA 0 Reserved 0x155 5:0 CLKin1_R[13:8] 0 The value of PLL1 N counter when CLKin1 is selected. Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 0x156 7:0 CLKin1_R[7:0] 150 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 LMK04832-SEP SNAS838 – OCTOBER 2022 www.ti.com 70 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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