LMK04832PAPSLASHEM datasheet(88/103 Pages) TI

88 / 103 page

9.2.1 Design Requirements

Clocks outputs:

• 1x 245.76-MHz clock for JESD204B/C ADC, LVPECL.

– This clock requires the best performance in this example.

• 2x 2949.12-MHz clock for JESD204B/C DAC, CML.

• 1x 122.88-MHz clock for JESD204B/C FPGA block, LVDS.

• 3x 10.24-MHz SYSREF for ADC (LVPECL), DAC (LVPECL), FPGA (LVDS).

• 2x 122.88-MHz clock for FPGA, LVDS.

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used.

9.2.2 Detailed Design Procedure

Note

This information is current as of the date of the release of this data sheet. Design tools receive

continuous improvements to add features and improve model accuracy. Refer to the software

instructions or training for latest features.

9.2.2.1 Device Selection

Enter the required frequencies into the tools. In this design, VCO0 and VCO1 both meet the design

requirements. VCO0 offers a relatively improved VCO performance over VCO1. In this case, choose VCO0

for improved RMS jitter in the 12-kHz to 20-MHz integration range.

9.2.2.1.1 Clock Architect

Under the advanced tab of the Clock Architect, filtering of specific parts can be done using regular expressions

in the Part Filter box. [LMK04832.*] will filter for only the LMK04832 device (without brackets). More detailed

filters can be given such as the entire part name LMK04832_VCO0 to force an LMK04832 using VCO0 solution

if one is available.

9.2.2.2 Device Configuration and Simulation

The tools automatically configure the simulation to meet the input and output frequency requirements given, and

make assumptions about other parameters to give some default simulations. However, the user may chose to

make adjustments for more accurate simulations to their application. For example:

• Entering the VCO Gain of the external VCXO or possible external VCO used device.

• Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents

result in smaller components but may increase impacts of leakage and at the lowest values reduce PLL

phase noise performance.

• Clock Architect allows loading a custom phase noise plot for reference or VCXO block. Typically, a custom

phase noise plot is entered for CLKin to match the reference phase noise to device; a phase noise plot for

the VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in

simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application.

• The PLLatinum™ Simulation tool can also be used to design and simulate a loop filter.

9.2.2.3 Device Programming

Using the clock design tools configuration the TICS Pro software is manually updated with this information to

meet the required application.

Frequency planning for assignment of outputs:

• To minimize crosstalk perform frequency planning / CLKOUT assignments to keep common frequencies on

outputs close together.

• It is best to place common device clock output frequencies on outputs sharing the same VCC group. For

example, these outputs share Vcc4_CG2. Refer to the Pin Configuration and Functions section to see the

VCC groupings the clock outputs.

LMK04832-SEP

SNAS838 – OCTOBER 2022

www.ti.com

Submit Document Feedback

Product Folder Links: LMK04832-SEP

LMK04832PAP/EM Datasheet(PDF) 88 Page - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 88 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL