LMK04832PAPSLASHEM datasheet(82/103 Pages) TI

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8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST

Table 8-81. Register 0x182

BIT

NAME

POR DEFAULT

DESCRIPTION

7:2

Reserved

CLR_PLL1_LD_LOST

To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.

0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge.

1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL1_LD_LOST to become set again.

CLR_PLL2_LD_LOST

To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.

0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge.

1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL2_LD_LOST to become set again.

8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD

For PLL2 DLD read back to be valid, either PLL2 DLD or PLL1 + PLL2 DLD signal must be output from the

status pins, or PLL2_DLD_EN bit must be set = 1.

Table 8-82. Register 0x183

BIT

NAME

POR DEFAULT

DESCRIPTION

7:4

N/A

Reserved

RB_PLL1_LD_LOST

This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD

is low.

RB_PLL1_LD

Read back 0: PLL1 DLD is low.

Read back 1: PLL1 DLD is high.

RB_PLL2_LD_LOST

This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD

is low.

RB_PLL2_LD

PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid

reading of this bit.

Read back 0: PLL2 DLD is low.

Read back 1: PLL2 DLD is high.

LMK04832-SEP

SNAS838 – OCTOBER 2022

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