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LMK04832PAP/EM Datasheet(PDF) 75 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 103 page  8.6.2.8 (0x160 - 0x16E) PLL2 Configuration 8.6.2.8.1 PLL2_R Table 8-68. PLL2_R[11:0] MSB LSB 0x160[3:0] / PLL2_R[11:8] 0x161[7:0] / PLL2_R[7:0] This register contains the value of the PLL2 R divider. Table 8-69. Registers 0x160 and 0x161 REGISTER BIT NAME POR DEFAULT DESCRIPTION 0x160 7:4 NA 0 Reserved 0x160 3:0 PLL2_R[11:8] 0 Valid values for the PLL2 R divider. Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 0x161 7:0 PLL2_R[7:0] 2 2 (0x02) 2 3 (0x03) 3 ... ... 4,094 (0xFFE) 4,094 4,095 (0xFFF) 4,095 www.ti.com LMK04832-SEP SNAS838 – OCTOBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: LMK04832-SEP |
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