LMK04832PAPSLASHEM datasheet(89/103 Pages) TI

89 / 103 page

In this example, the 245.76-MHz ADC output needs the best performance. CLKOUT2 provides the best noise

floor / performance. The 245.76 MHz is placed on CLKOUT2 with 10.24-MHz SYSREF on CLKOUT3.

• For best performance the input and output drive level bits may be set. Best noise floor performance is

achieved with CLKout2_3_IDL = 1 and CLKout2_3_ODL = 1.

• The CLKoutX_Y_ODL bit has no impact on even clock outputs in high performance bypass mode.

In this example, the 983.04-MHz DAC output is placed on CLKOUT4 and CLKOUT6 with 10.24-MHz SYSREF

on paired CLKOUT5 and CLKOUT7 outputs.

• These outputs share Vcc4_CG2.

In this example, the 122.88-MHz FPGA JESD204B/C output is placed on CLKOUT10 with 10.24-MHz SYSREF

on paired CLKOUT11 output.

Additionally, the 122.88-MHz FPGA non-JESD204B/C outputs are placed on CLKOUT8 and CLKOUT9.

• When frequency planning, consider PLL2 as a clock output at the phase detector frequency. As such, these

122.88-MHz outputs have been placed on the outputs close to the PLL2 and Charge Pump power supplies.

Once the device programming is completed as desired in the TICS Pro software, it is possible to export the

9.3 Power Supply Recommendations

9.3.1 Current Consumption

Current consumption varies considerably with the number of outputs and output formats.

9.4 Layout

9.4.1 Layout Guidelines

In general, the following general guidelines are useful to keep in mind.

• GND pins on the outer perimeter of the package may be routed on the package back to the DAP

• Ensure the DAP on device is well-grounded with many vias.

• Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.

• For power supply bypassing, isolate each clock group .

In addition to this, there are special considerations for the routing of the outputs. The outputs are divided in to

several output groups.

• Clock Group 0: CLKOUT0, CLKOUT1, CLKOUT12, CLKOUT13

• Clock Group 1: CLKOUT2, CLKOUT3

• Clock Group 2: CLKOUT4, CLKOUT5, CLKOUT6, CLKOUT7

• Clock Group 3: CLKOUT8, CLKOUT9, CLKOUT10, CLKOUT11

It is optimal to isolate the power supply pins for these clock group pins with a ferrite bead to crosstalk between

the outputs, especially if the output groups have different frequencies. If there is flexibility in planning which

frequencies go to which outputs, crosstalk can be minimized by putting different frequencies in different output

groups (as opposed to putting them in the same output group).

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 89 Page - Texas Instruments