LMK04832PAPSLASHEM datasheet(84/103 Pages) TI

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

To assist customers in frequency planning and design of loop filters, Texas Instruments provides Clock Architect

and PLLatinum Sim and on ti.com.

9.1.1 Treatment of Unused Pins

Not all pins are needed for every application. In general, power down the unused feature in software. The

unused pin may be left floating or grounded through a 1-kΩ resistor.

Table 9-1. Treatment of Unused Pins

PINS

TREATMENT IF UNUSED

CLKOUTx_P/CLKOUTx_N

1 kΩ to GND or float pin

RESET/GPO

1 kΩ to GND or float pin

SYNC/SYSREF_REQ

1 kΩ to GND or float pin

FIN0_P/FIN0_N

1 kΩ to GND or float pin

STATUS_LD1,STATUS_LD2

1 kΩ to GND or float pin

CPOUT1,CPOUT2

1 kΩ to GND or float pin

OSCOUT_P/CLKIN2_P

1 kΩ to GND or float pin

OSCOUT_N/CLKIN2_N

1 kΩ to GND or float pin

9.1.2 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A

window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback

signals of the PLL for each event to occur. When a PLL digital lock event occurs, the digital lock detect

of the PLL is asserted true. When the holdover exit event occurs, the device will exit holdover mode when

HOLDOVER_EXIT_MODE = 1 (Exit based on DLD).

Table 9-2. Digital Lock Detect Related Fields

EVENT

PLL

WINDOW SIZE

LOCK COUNT

PLL1 Locked

PLL1

PLL1_WND_SIZE

PLL1_DLD_CNT

PLL2 Locked

PLL2

PLL2_WND_SIZE

PLL2_DLD_CNT

Holdover exit

PLL1

PLL1_WND_SIZE

HOLDOVER_DLD_CNT

For a digital lock detect event to occur, there must be a lock count number of phase detector cycles of PLLX

during which the time and phase error of the PLLX_R reference and PLLX_N feedback signal edges are within

the user programmable window size. There must be at least one lock count phase detector event before a lock

event occurs, therefore a minimum digital lock event time can be calculated as lock count / fPDX where X = 1 for

PLL1 or 2 for PLL2.

By using Equation 4, values for a lock count and window size can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × fPDX

PLLX_DLD_CNT

ppm =

(4)

LMK04832-SEP

SNAS838 – OCTOBER 2022

www.ti.com

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