LMK04832PAPSLASHEM datasheet(42/103 Pages) TI

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8.6.2 Device Register Descriptions

The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions

of each bit.

In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as

X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to

13. In the case where X and Y are both used in a bit name, then Y = X + 1.

8.6.2.1 System Functions

8.6.2.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function and the ability to turn off 3-wire SPI mode. To use a 4-wire SPI mode,

selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX or RESET_MUX. It

is possible to have 3-wire and 4-wire readback at the same time.

Table 8-7. Register 0x000

BIT

NAME

POR DEFAULT

DESCRIPTION

RESET

0: Normal operation

1: Reset (automatically cleared)

6:5

Reserved

SPI_3WIRE_DIS

Disable 3-wire SPI mode.

0: 3 Wire Mode enabled

1: 3 Wire Mode disabled

3:0

Reserved

8.6.2.1.2 POWERDOWN

This register contains the POWERDOWN function.

Table 8-8. Register 0x002

BIT

NAME

POR DEFAULT

DESCRIPTION

7:1

Reserved

POWERDOWN

0: Normal operation

1: Power down device.

8.6.2.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

Table 8-9. Register 0x003

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

ID_DEVICE_TYPE

PLL product device type.

LMK04832-SEP

SNAS838 – OCTOBER 2022

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