LMK04832PAPSLASHEM datasheet(18/103 Pages) TI

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Note

The FIN0_P/FIN0_N input is generally recommended because it is lower noise, supports higher input

frequency (up to 6 GHz if the div2 is used), and it leaves CLKIN1 available for redundant inputs.

FIN1_P/FIN1_N inputs are generally NOT recommended, for the reasons stated above, although they

can be used.

8.1.5 Clock Distribution

There are a total of 14 PLL2 clock outputs driven from the internal or external VCO.

All clock outputs have programmable output types. They can be programmed to CML, LVPECL, LVDS, HSDS, or

LCPECL. All odd clock outputs plus CLKOUT8 and CLKOUT10 may be programmed to LVCMOS.

In addition to these 14 clocks, there is also an additional OSCout output for a total of 15 differential. OSCout

may be a buffered version of OSCIN, DCLKOUT6, DCLKOUT8, or SYSREF. Its output format is programmable

to LVDS, LVPECL, or LVCMOS.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.5.1 Clock Divider

There are seven clock dividers. In a traditional clocking system, each divider can drive two outputs. The divider

range is 1 to 1023. Duty cycle correction may be enabled for the output. When the divider is used even clocks

may not output CML.

In a JESD204B/C system, one clock output is a device clock driven from the clock divider and the other paired

clock is from the SYSREF divider. For connectivity flexibility, either the even or odd clock output may be driven

by the clock divider or be the SYSREF output.

8.1.5.2 High Performance Divider Bypass Mode

The even clock outputs (CLKOUT0/2/4/6/8/10/12) may bypass the clock divider to achieve the best possible

noise floor and output swing. In this mode, the only usable output format is CML.

8.1.5.3 SYSREF Clock Divider

The SYSREF divider supports a divide range of 8 to 8191 (even and odd). There is no duty cycle correction for

the SYSREF divider. The SYSREF output may be routed to all clock outputs.

8.1.5.4 Device Clock Delay

The device clocks support digital delay for phase adjustment of the clock outputs.

The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as

half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The digital delay value takes effect on the clock output phase after a SYNC event.

8.1.5.5 Dynamic Digital Delay

The device clock dividers support a dynamic digital delay feature which allows the clock to be delayed by one full

device clock cycle. With a single programming, an adjustment of up to 255 one cycle delays may occur. When

making a multi-step adjustment, the adjustments are periodically applied to reduce impact to the clock.

Dynamic phase adjustments of half a clock distribution cycle are possible by half step.

The SYSREF digital delay value is reused for dynamic digital delay. To achieve a one cycle delay program the

SYSREF digital delay value to one greater than half the SYSREF divide value.

8.1.5.6 SYSREF Delay: Global and Local

The SYSREF divider includes a digital delay block which allows a global phase shift with respect to the device

clocks.

LMK04832-SEP

SNAS838 – OCTOBER 2022

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