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LMK04832PAP/EM Datasheet(PDF) 9 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 103 page  VDD, VDD_A = 3.3 V ± 5 %, –55°C ≤TA ≤ 125°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |ΔTCL| Allowable temperature Drift for Continuous Lock(7) VCO0 150 oC Allowable temperature Drift for Continuous Lock(7) VCO1 180 oC L(f)VCO Open Loop VCO Phase Noise VCO0 at 2440 MHz 10 kHz –88.4 dBc/Hz 100 kHz –117 800 kHz –137.5 1 MHz –139.7 10 MHz –152.6 VCO0 at 2580 MHz 10 kHz –85.7 100 kHz –115.8 800 kHz –137 1 MHz –138.6 10 MHz –151.8 L(f)VCO Open Loop VCO Phase Noise VCO1 at 2945 MHz 10 kHz –82.6 dBc/Hz 100 kHz –112.3 800 kHz –134.9 1 MHz –137.2 10 MHz –151.1 VCO1 at 3250 MHz 10 kHz –81 100 kHz –110.4 800 kHz –134.3 1 MHz –135.6 10 MHz –149.3 Output Clock Skew and Timing SKEWCLKOU TX Output to Output Skew Same Pair of Device clocks and same format 50 ps Even to Even or Odd to Odd, Same Format 50 Even clock to Odd Clock 50 Additive Jitter in Distribution Mode from FIN Pin (note 6) L(f)CLKOUT Additive jitter, Distribution mode with no divide 245.76 MHz Output Frequency, 12k-20MHz integration bandwidth LVCMOS 50 fs LVDS 50 LVPECL 40 LCPECL 35 HSDS 40 CML 35 LVCMOS Outputs fCLKOUT Frequency 5 pF Load 250 MHz L(f)CLKOUT Noise Floor 245.76 MHz 20 MHz Offset –160 dBc/Hz VOH Output High Voltage 1 mA load Vcc–0.1 V VOL Output Low Voltage 1 mA load 0.1 V IOH Output High Current FD=1.65V –28 mA IOL Output Low Current Vd=1.65V 28 mA ODC Output Duty Cycle 50 % LVDS Clock Outputs L(f)CLKOUT Noise Floor 245.76 MHz output 20 MHz Offset –159.5 dBc/Hz TR/TF 20% to 80% Rise/Fall Time 175 ps www.ti.com LMK04832-SEP SNAS838 – OCTOBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMK04832-SEP |
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