LMK04832PAPSLASHEM datasheet(67/103 Pages) TI

67 / 103 page

8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is

entered.

Table 8-50. Register 0x14E

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

DAC_CLK_MULT

This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the

DAC value is tracked.

Field Value

DAC Multiplier Value

0 (0x00)

1 (0x01)

2 (0x02)

1024

3 (0x03)

16384

5:0

DAC_TRIP_HIGH

Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is

enabled.

Field Value

DAC Trip Value

0 (0x00)

1 x Vcc / 64

1 (0x01)

2 x Vcc / 64

2 (0x02)

3 x Vcc / 64

3 (0x03)

4 x Vcc / 64

...

61 (0x17)

62 x Vcc / 64

62 (0x18)

63 x Vcc / 64

63 (0x19)

64 x Vcc / 64

8.6.2.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

Table 8-51. Register 0x14F

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

DAC_CLK_CNTR

127

This with DAC_CLK_MULT set the rate at which the DAC is updated. The

update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF

Field Value

DAC Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

253 (0xFD)

253

254 (0xFE)

254

255 (0xFF)

255

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LMK04832-SEP

SNAS838 – OCTOBER 2022

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LMK04832PAP/EM Datasheet(PDF) 67 Page - Texas Instruments

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