LMK04832PAPSLASHEM datasheet(78/103 Pages) TI

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8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

Table 8-75. Register 0x169

BIT

NAME

POR DEFAULT

DESCRIPTION

Reserved

6:5

PLL2_WND_SIZE

PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2.

If the phase error between the reference and feedback of PLL2 is less than

specified time, then the PLL2 lock counter increments.

Field Value

Maximum Phase Detector

Frequency / Window Size

0 (0x00)

Reserved

1 (0x01)

320 MHz / 1 ns

2 (0x02)

240 MHz / 1.8 ns

3 (0x03)

160 MHz / 2.6 ns

4:3

PLL2_CP_GAIN

This bit programs the PLL2 charge pump output current level. The table

below also shows the impact of the PLL2 TRISTATE bit in conjunction with

PLL2_CP_GAIN.

Field Value

Definition

0 (0x00)

Reserved

1 (0x01)

Reserved

2 (0x02)

1600 µA

3 (0x03)

3200 µA

PLL2_CP_POL

PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO

requires the negative charge pump polarity to be selected. Many VCOs use

positive slope.

A positive slope VCO increases output frequency with increasing voltage. A

negative slope VCO decreases output frequency with increasing voltage.

Field Value

Description

Negative Slope VCO/VCXO

Positive Slope VCO/VCXO

PLL2_CP_TRI

PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.

0: Disabled

1: TRI-STATE

PLL2_DLD_EN

PLL2 DLD circuitry is enabled when the PLL2 DLD is used to provide an output

to a lock detect status pin. PLL2_DLD_EN allows enabling the PLL2 DLD

circuitry without needing to provide PLL2 DLD to a status pin. This enables

PLL2 DLD status to be read back using SPI while allowing the Status pins to

be used for other purposes.

0: PLL2 DLD circuitry is on only of PLL2 DLD or PLL1 + PLL2 DLD signal is

output from a Status_LD_MUX.

1: PLL2 DLD circuitry is forced on.

LMK04832-SEP

SNAS838 – OCTOBER 2022

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