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LMK04832PAP/EM Datasheet(PDF) 11 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 103 page  VDD, VDD_A = 3.3 V ± 5 %, –55°C ≤TA ≤ 125°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOD Output Voltage 50 Ω pull up to Vcc, DC Measurement CML 16 mA 840 mV CML 24 mA 1260 CML 32 mA 1660 50 Ω pull up to Vcc, DC Measurement, RL = AC coupled 100 Ω, 250 MHz CML 16 mA 550 mV CML 24 mA 815 CML 32 mA 1070 Digital Outputs (CLKin_SELX,STATUS_LDX, and RESET/GPO,SDIO) VOH Output High Voltage Vcc–0.4 V VOL Output Low Voltage 0.4 V Digital Inputs VIH High-level input voltage 1.2 V VIL Low-level input voltage 0.5 V IIH High-level input current RESET/GPO,SYNC,SCK,SDIO, CS# 10 80 uA SYNC VIH = VCC 25 IIL Low-level input current CLKINX_SEL,RESET/GPO,SYNC,SCK,SDIO, CS# –5 5 uA IIL Low-level input current SYNC VIL = 0 V –5 5 (1) Use the TICS Pro tool to calculate Icc for a specific configuration (2) Device will function with slew rate as low as 0.15 V/ns, however a slew rate of 0.5 V/ns or higher is recommended to get the best phase noise performance. (3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. (4) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = LPLL_flicker(10 kHz) - 20 log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f) (5) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1 HZ = LPLL_flat(f) - 20 log(N) - 10 log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). (6) This parameter is programmable to more states than are shown in the electrical specifications (7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. This parameter is indirectly tested. 6.6 Timing Requirements VDD, VDD_A = 3.3 V ± 5 %, –55°C ≤TA ≤ 125°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise noted) SYMBOL PARAMETER MIN NOM MAX UNIT Timing Requirements tdS Setup time for SDI edge to SCK rising edge 40 ns tdH Hold time for SDI edge to SCK rising edge 20 ns tSCK Period of SCK 400 ns tHIGH High width of SCK 120 ns tLOW Low width of SCK 120 ns tCS Setup time for CS# falling edge to SCK rising edge 40 ns tCH Hold time for CS# rising edge from SCK rising edge 40 ns tDV SCK falling edge to valid read back data 120 ns www.ti.com LMK04832-SEP SNAS838 – OCTOBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMK04832-SEP |
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