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LMK04832PAP/EM Datasheet(PDF) 83 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 103 page  8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs are shared with the RB_DAC_VALUE. See the RB_DAC_VALUE section for more information. Table 8-83. Register 0x184 BIT NAME POR DEFAULT DESCRIPTION 7:6 RB_DAC_VALUE[9:8] See the RB_DAC_VALUE section. 5 RB_CLKin2_SEL Read back 0: CLKin2 is not selected for input to PLL1. Read back 1: CLKin2 is selected for input to PLL1. 4 RB_CLKin1_SEL Read back 0: CLKin1 is not selected for input to PLL1. Read back 1: CLKin1 is selected for input to PLL1. 3 RB_CLKin0_SEL Read back 0: CLKin0 is not selected for input to PLL1. Read back 1: CLKin0 is selected for input to PLL1. 2 N/A 1 RB_CLKin1_LOS Read back 1: CLKin1 LOS is active. Read back 0: CLKin1 LOS is not active. 0 RB_CLKin0_LOS Read back 1: CLKin0 LOS is active. Read back 0: CLKin0 LOS is not active. 8.6.2.9.6 RB_DAC_VALUE Contains the value of the DAC for user readback. Table 8-84. RB_DAC_VALUE[9:0] MSB LSB 0x184 [7:6] / RB_DAC_VALUE[9:8] 0x185 [7:0] / RB_DAC_VALUE[7:0] Table 8-85. Registers 0x184 and 0x185 REGISTER BIT NAME POR DEFAULT 0x184 7:6 RB_DAC_ VALUE[9:8] 2 DAC value is 512 on power on reset, if PLL1 locks upon power-up the DAC value will change. 0x185 7:0 RB_DAC_ VALUE[7:0] 0 8.6.2.9.7 RB_HOLDOVER Table 8-86. Register 0x188 BIT NAME POR DEFAULT DESCRIPTION 7:5 N/A Reserved 4 RB_HOLDOVER Read back 0: Not in HOLDOVER. Read back 1: In HOLDOVER. 3:0 N/A Reserved 8.6.2.9.8 SPI_LOCK Prevents SPI registers from being written to, except for 0x555. This register cannot be read back. Table 8-87. Register 0x555 BIT NAME POR DEFAULT DESCRIPTION 7:0 SPI_LOCK 0 0: Registers unlocked. 1 to 255: Registers locked. www.ti.com LMK04832-SEP SNAS838 – OCTOBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: LMK04832-SEP |
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