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LMK04832PAP/EM Datasheet(PDF) 64 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 103 page ![]() 8.6.2.5 RESET_MUX, RESET_TYPE This register contains control of the RESET pin. Table 8-46. Register 0x14A BIT NAME POR DEFAULT DESCRIPTION 7:6 NA 0 Reserved 5:3 RESET_MUX 0 This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an output mode. Field Value Output Format 0 (0x00) Logic Low 1 (0x01) Reserved 2 (0x02) CLKin2 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback 2:0 RESET_TYPE 2 This sets the IO type of the RESET pin. Field Value Configuration Function 0 (0x00) Input Reset Mode Reset pin high = Reset 1 (0x01) Input with pullup resistor 2 (0x02) Input with pulldown resistor 3 (0x03) Output (push-pull) Output modes; see the RESET_MUX register for description of outputs. 4 (0x04) Output inverted (push- pull) 5 (0x05) Reserved 6 (0x06) Output (open-drain) LMK04832-SEP SNAS838 – OCTOBER 2022 www.ti.com 64 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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