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IP175DLF Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 20 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
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August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
Pin description
(continued)
Pin No.
Label
Type
Description
External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0)
89
MII0_RXCLK
O
MII receive clock
MII0_RXCLK and MII0_TXCLK are the same clock source and
in phase.
81
MII0_TXCLK
O
MII transmit clock
80, 79,
78, 77
TXD0_0,
TXD0_1,
TXD0_2, TXD0_3
I
MII transmit data
It is sampled at the rising edge of MII0_TXCLK.
76
TXEN0
I
MII transmit enable
It is used to frame TXD0[3:0]. It is sampled at the rising edge of
MII0_TXCLK.
90
COL0
O
MII collision
It is active when MII0 is half duplex and a collision event happens.
84
RXDV0
O
MII receive data valid
It is used to frame RXD0[3:0]. It is sent out at the falling edge of
MII0_RXCLK.
88, 87,
86, 85
RXD0_0, RXD0_1,
RXD0_2, RXD0_3
O
MII receive data
It is sent out at the falling edge of MII0_RXCLK.



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