IP175DLF datasheet(61/145 Pages) ETC

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IP175DLF

Datasheet

61/145

August 22, 2014

IP175DLF-DS-R10.1

R/W = Read/Write, SC = Self-Clearing, RO = Read Only, LL = Latching Low, LH = Latching High.

4.3

MII Register 0

4.3.1

MII Register 0 of PHY0~4

(Each PHY has its own MII register 0 with different PHY address)

PHY

MII

ROM

R/W

Description

Default

Control register

4~0

0.15

RW/

Reset

The PHY is reset if user write “1” to this bit. The reset period is

around 2ms. User has to wait for at least 2ms to access

IP175DLF.

4~0

0.14

R/W Loop back

1 = Loop back mode

0 = normal operation

When this bit set, IP175DLF will be isolated from the network

media, that is, the assertion of TXEN at the MII will not transmit

data on the network. All MII transmission data will be returned

to MII receive data path in response to the assertion of TXEN.

Bit 0.12 is cleared automatically, if this bit is set. User has to

program bit 0.12 again after loop back test.

4~0

0.13

RW Speed Selection

1 = 100Mbps

0 = 10Mbps

It is valid only if bit 0.12 is set to be 0.

4~0

0.12

RW Auto-Negotiation Enable

1 = Auto-Negotiation Enable

0 = Auto-Negotiation Disable

MII register 4~0.22 Auto MDI-MDIX should be disabled if

Auto-Negotiation is disabled.

4~0

0.11

R/W Power Down

1: power down mode

0: normal operation

4~0

0.10

Isolate

IP175DLF doesn’t support this function.

4~0

0.9

Restart Auto- Negotiation

1 = re-starting Auto-Negotiation

0 = normal operation

4~0

0.8

R/W Duplex mode

1 = full duplex

0 = half duplex

It is valid only if bit 0.12 is set to be 0.

4~0

0.7

R/W Collision test

4~0

0[6:0]

Reserved

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