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IP175DLF Datasheet(PDF) 99 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 99 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
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August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
5.4.4
MII0, MII1 and MII2 Control Register 1
PHY
MII
ROM
R/W
Description
Default
3[15]
44[7]
R/W P4EXT
1: enable
0: disable (default)
pin 74
(0)
3[14]
--
RO
SMI0_POLLING
1: MII0 MAC mode
0: MII0 PHY mode
1’b0
3[13]
--
RO
SMI1_POLLING
1: MII1 MAC mode
0: MII1 PHY mode
1’b0
3[12]
44[6]
R/W MII1_PHY_MODE
1: MII1 is connected to PHY4.0: MII1 is connected to MAC4.
pin 54
(1)
MII0_MAC_MODE_EN
External MII0 port MAC mode
1: MII0 works as a MAC and should be connected to an
external PHY.
0: MII0 works as a PHY and should be connected to an
external MAC device (default).
This bit does not affect MII1 port.
Default Value
MII2_EN=1
MII2_EN=0
3[11]
44[5]
R/W
0
Pin96 MII0_MAC_MODE (0)
*
MII0_RMII_EN (RMII_EN)
1: MII0 RMII interface enabled
0: MII0 RMII interface disabled (default).
Default Value
P4EXT=1 & RMII_EN=1
Others
3[10]
44[4]
R/W
1
0
pin
53
(0)
MII2_RMII_EN (MII1OR2_RMII_EN)
1: MII2 RMII interface enabled
0: MII2 RMII interface disabled (default).
Default Value
P4EXT=1 & RMII_EN=1 & MII2_EN=1
Others
3[9]
44[3]
R/W
1
0
*
MII1_RMII_EN (PHY4_RMII_EN)
1: MII1 RMII interface enabled
0: MII1 RMII interface disabled (default).
Default Value
P4EXT=1 & RMII_EN=1 & MII1_DIS=0
Others
3[8]
44[2]
R/W
1
0
*
3[7]
44[1]
R/W MII1OR2_MAC_REPEATER
1: external PHY ‘s TXEN does not loop back to CRS (default)
0: external PHY ‘s TXEN loop back to CRS
1’b1
21
3[6]
44[0]
R/W MII0_MAC_REPEATER
1: external PHY ‘s TXEN does not loop back to CRS (default)
0: external PHY ‘s TXEN loop back to CRS
1’b1



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