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IP175DLF Datasheet(PDF) 33 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 33 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
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August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
Pin description (continued)
Pin No.
Label
Type
Description
Misc.
123
X1
I
System clock input or crystal input
It is recommended to connect X1 and X2 to a crystal. If the clock
source is from another chip, the clock should be active at least
for 1ms before pin 93 RESETB de-asserted.
122
X2
O
Crystal output
93
RESETB
I
Reset, low active
52
TEST2
IPL
Test mode enable
It should be connected to GND for normal operation.
116
CRS2
IPL
Carrier sense of MII2 (home plug application)
It is valid only if CRS_EN is pull high
It is an input signal and is connected to MII_CRS of external
PHY.
43
CRS1
IPL
Carrier sense of MII1 (home plug application)
It is valid only if CRS_EN is pull high
It is an input signal and is connected to MII_CRS of external
PHY.
44
CRS0
IPL
Carrier sense of MII0 (home plug application)
It is valid only if CRS_EN is pull high
It is an input signal and is connected to MII_CRS of external
PHY.
42
INT
IPL2/
O
Interrupt output
It can be either active low or high by writing MII register
21.20[15]
EEPROM (only 24C02, 24C04, 24C08 & 24C16 supported)
53
SCL
IPL2/
O
After reset, it is used as clock pin SCL of EEPROM. Its period is
longer than 10us. IP175DLF stops reading EEPROM if it finds
there is no 55AA pattern in address 0. After reading EEPROM,
this pin becomes an input pin.
54
SDA
IPH2/
O
After reset, it is used as data pin SDA of EEPROM. After reading
EEPROM, this pin becomes an input pin. It is pulled up in
EEPROM application circuit.
SMI
71,
70
MDC0,
MDIO0
IPL,
IPL2
SMI0
The external MAC device uses the interface to access
IP175DLF’s MII registers.



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