IP175DLF datasheet(64/145 Pages) ETC

Part #	IP175DLF

Description	5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)

PDF	145 Pages

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Manufacturer	ETC [List of Unclassifed Manufacturers]

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64 / 145 page

IP175DLF

Datasheet

64/145

August 22, 2014

IP175DLF-DS-R10.1

PHY

MII

ROM

R/W

Description

Default

Status register

4~0

1.2

Link Status

1 = Link Pass

0 = Link Fail

When read as logic 1, indicates that IP175DLF has determined

a valid link has been established. When read as logic 0,

indicates the link is not valid. This bit is cleared until a valid link

has been established and before reading the contents of this

registers.

4~0

1.1

Jabber Detect

1 = jabber condition detected

0 = no jabber condition detected

When read as logic 1, indicates that IP175DLF has detected a

jabber condition. This bit is always 0 for 100Mbps operation

and is cleared after IP175DLF reset. When the duration of

TXEN exceeds the jabber timer (21ms), the transmission and

loop back functions will be disabled and the COL is active. After

TXEN goes low for more than 500 ms, the transmitter will be

re-enabled.

4~0

1.0

Extended capability

1 = Extended register capabilities

0 = No extended register capabilities

IP175DLF has extended register capabilities.

IP175DLF Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers