IP175DLF datasheet(42/145 Pages) ETC

Part #	IP175DLF

Description	5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)

PDF	145 Pages

Scroll/Zoom	100%

Manufacturer	ETC [List of Unclassifed Manufacturers]

Direct Link

Logo

42 / 145 page

IP175DLF

Datasheet

42/145

August 22, 2014

IP175DLF-DS-R10.1

MII2 PHY mode

EEPROM

MII register

Name

Reg

Name

Phy

Reg

MII2 speed

MAC4_F_100

MAC4_FORCE_100

2.6

MAC4_FORCE_100

4.14

MII2 duplex

MAC4_F_FULL

MAC4_FORCE_FULL

2.4

MAC4_FORCE_FULL

4.12

MII2 pause

MAC_X_EN

3.0

MAC_X_EN

5.0

MII2 MAC mode: There are two ways to set MII2 speed, duplex and pause.

1. IP175DLF reads the MII registers 0~5 of external PHY through MDC1, MDIO1.

MII2

Speed

Duplex

Pause

IP175DLF polls the external PHY with address defined in MII register

21.2[4:0]. The default address value is 00001.

After reset, IP175DLF writes the speed/duplex/pause capability to the external

PHY using the content of MII register 21.2[12:8].

IP175DLF reads MII register 0~5 of external PHY as MII2 speed, duplex and

pause continuously.

2. Force mode (MDC1 and MDIO1 are not connected to external PHY)

EEPROM

MII register

Name

Reg

Name

Phy

Reg

MII2 speed

MAC4_F_100

MAC4_FORCE_100

2.6

MAC4_FORCE_100

4.14

MII2 duplex

MAC4_F_FULL

MAC4_FORCE_FULL

2.4

MAC4_FORCE_FULL

4.12

MII2 pause

MAC_X_EN

3.0

MAC_X_EN

5.0

IP175DLF Datasheet(PDF) 42 Page - List of Unclassifed Manufacturers

IP175DLF Datasheet(HTML) 42 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL