IP175DLF datasheet(41/145 Pages) ETC

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IP175DLF

Datasheet

41/145

August 22, 2014

IP175DLF-DS-R10.1

MII1 PHY mode: In MII1 PHY mode, the MII1 interface connects to 5

th PHY in IP175DLF and this PHY

address is 4. The external device can read this PHY’s MII management registers via MID1/MDIO1.

EEPROM

MII register

Name

Reg

Name

Phy

Reg

MII1

speed/duplex/

pause

0~5

MII1 MAC mode: There are two ways to set MII1’s speed, duplex and pause.

1. IP175DLF reads the MII registers 0~5 of external PHY through MDC1, MDIO1.

MII1

Speed

Duplex

Pause

IP175DLF polls the external PHY with address defined in MII register

21.2[4:0]. The default address value is 00001.

After reset, IP175DLF writes the speed/duplex/pause capability to the external

PHY using the content of MII register 21.2[12:8].

IP175DLF reads MII register 0~5 of external PHY as MII1 speed, duplex and

pause continuously.

2. Force mode (MDC1 and MDIO1 are not connected to external PHY)

EEPROM

MII register

Name

Reg

Name

Phy

Reg

MII1 speed

MAC4_F_100

MAC4_FORCE_100

2.6

MAC4_FORCE_100

4.14

MII1 duplex

MAC4_F_FULL

MAC4_FORCE_FULL

2.4

MAC4_FORCE_FULL

4.12

MII1 pause

MAC_X_EN

3.0

MAC_X_EN

5.0

IP175DLF Datasheet(PDF) 41 Page - List of Unclassifed Manufacturers

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